The very large scale integrated (VLSI) circuits fabricated today typically contain hundreds of thousands of circuit elements. Testing these complex circuits to isolate faulty circuits from fault-free circuits has become increasingly difficult because of the inaccessibility of internal circuit elements and the elements' interdependencies. Furthermore, as the number of possible test paths through a circuit rises at 2n, where n is the number of circuit elements, efficient testing will continue to increase in difficulty as the density of these circuits continues to grow.
To test a circuit, a set of test vectors, or patterns, must be developed. The circuit is simulated without faults and the test patterns are applied to determine the circuit's expected response to the patterns at its primary outputs. The circuit is then simulated with faults and the test patterns are again applied to determine if there is a change in the expected response to any pattern at the outputs. A fault that does not cause a change in the expected (fault free) response is an undetected fault. A test procedure desirably detects a high percentage of faults, and thus should have a minimum of undetected faults.
One common method of developing tests employs external automated test equipment (ATE). In this method, an automatic test pattern generator (ATPG) is used which, given a circuit and fault model, generates a set of test patterns designed to detect close to 100% of the circuit's faults. These deterministic test patterns are then compressed and stored in a tester. During testing, they are decompressed and loaded into the primary inputs of the circuit under test (CUT). Faults are detected by comparing the response of the circuit to the expected response.
An example of an ATE environment is described in U.S. Patent Application Publication No. 2007/0011530-A1, which is hereby incorporated by reference. Such publication describes that an external ATE supplies compressed test patterns on scan channels to the integrated circuit under test. These test patterns are then decompressed and provided to scan chains to test the integrated circuit. Specific examples of decompressors and compactors are provided.
Although deterministic ATPG can detect close to 100% of faults, it requires enormous resources to generate and store the test patterns required for complex VLSI circuits. Furthermore, interactions between the external tester and elements in the CUT create their own set of potential errors.
To counter these problems, built-in self-test (BIST) methods have been developed that move the test pattern generation and output response analysis from an external source onto the chip itself. For certain BIST technologies, rather than using a set of test patterns specifically defined to detect a known set of faults, a pseudo-random pattern generator (PRPG), generally a linear feedback shift register (LFSR), on the chip itself generates pseudo-random patterns, which are then used to detect faults. Typically, the LFSR includes interconnected memory elements (such as flip-flops) and linear logic elements (such as XOR or XNOR gates). On-chip output response analysis is typically performed by a multiple-input-shift-register (MISR) or other circuit that compacts the output response and generates a signature for comparison with the signature of a fault-free circuit.
Although pseudo-random pattern generation is simple, this method rarely achieves the close-to 100% fault detection achieved by ATPG, as there are almost always faults that require very specific patterns to test; these patterns often take many, many cycles to be automatically generated, thereby elevating the cost of test application and fault simulation beyond acceptable levels.
To tackle the problem of pseudo-random-pattern resistance, many techniques have been proposed, such as changing the attributes of the pseudo-random patterns to provide better fault coverage. Some of these techniques include reseeding, weighted random testing, and pattern mapping. In reseeding, deterministic test patterns are compressed and encoded as seeds for a PRPG. These seeds then generate test patterns known to find otherwise-undetectable faults. Weighted random testing uses mathematical methods to modify the pseudo-random patterns in ways that bias them toward detecting random-pattern-resistant faults by assigning weights to the values contained in specific scan cells, biasing their values towards “1” or “0”. Pattern mapping takes the set of patterns generated by the PRPG and transforms them, using on-chip logic, into a new set of deterministic patterns that provides the desired fault coverage. However, these methods are significantly more complicated than simple random pattern generation and either require extra memory to store the seeds or weight sets, or require additional logic, all of which is expensive in terms of area overhead.
Accordingly, there is still a need for a BIST solution that provides high fault coverage without unduly expensive logic overhead.